10/100/1000 Ethernet MAC

Publisher: Synflow

Status: FPGA Proven




Description

The Ethernet IP Core is a 10/100/1000 Media Access Controller (MAC). It consists of a FPGA proven Cx code that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 specifications.


Features

The core provides the following features:


Architecture

The general architecture of the Ethernet IP core consists of five main parts:


Modules

The macTopSend and macTopReceive modules provide full transmit and receive functionality. CRC generators are incorporated in both modules. The modules also handle preamble generation and removal. Padding occurs automatically (when enabled) in compliance with the IEEE 802.3 standard.

phyTop manages the standard IEEE 802.3 Media Independent Interface (MII) that defines the connection between the PHY and link layers. Using this interface, the device connected to the host interface automatically detect the speed of the Ethernet connection and the parameters (e.g. full-duplex, half-duplex).

Frame driver/echo, and Frame selector are used for tests only. They can be removed for production.


Interface

The core is connected directly to the application. Therefore, the application need to be able to receive a frame of data from the core any time and it must send frame of data to the core.


Status

The project is done and FPGA proven.