10/100/1000 Ethernet MAC
Status: FPGA Proven
The Ethernet IP Core is a 10/100/1000 Media Access Controller (MAC). It consists of a FPGA proven Cx code that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 specifications.
The core provides the following features:
- Flow control and automatic generation of control frames in full duplex mode (IEEE 802.3x)
- 32-bit CRC generation and checking
- Preamble generation and removal
- IEEE 802.3 Media Independent Interface (MII) and gigabit media-independent interface (GMII) implemented
- Direct Interconnection with the cocre
The general architecture of the Ethernet IP core consists of five main parts:
- macTopSend: it receives data from the application, processes it, and send it to the phy (Ethernet)
- macTopReceive: it receives data from the phy (Ethernet), processes it, and send it to the application
- phyTop: it manages the phy (MIIM) and detect the speed
- Frame driver/echo: both are frame generators to verify the behaviour of the core when deployed
- Frame selector: it allows the user to switch from normal mode to test mode
The macTopSend and macTopReceive modules provide full transmit and receive functionality. CRC generators are incorporated in both modules. The modules also handle preamble generation and removal. Padding occurs automatically (when enabled) in compliance with the IEEE 802.3 standard.
phyTop manages the standard IEEE 802.3 Media Independent Interface (MII) that defines the connection between the PHY and link layers. Using this interface, the device connected to the host interface automatically detect the speed of the Ethernet connection and the parameters (e.g. full-duplex, half-duplex).
Frame driver/echo, and Frame selector are used for tests only. They can be removed for production.
The core is connected directly to the application. Therefore, the application need to be able to receive a frame of data from the core any time and it must send frame of data to the core.
The project is done and FPGA proven.