Status: Ongoing project
the RISC-V core is an implementation of a reduced instruction set computing (RISC) based instruction set architecture (ISA). Most ISAs are commercially protected by patents, preventing practical efforts to reproduce the computer systems. In contrast, RISC-V is open, permitting any person or group to construct compatible computers, and use associated software.
The core provides the following features:
- 3-operand load-store architecture
- 32 general-purpose registers
- 32-bit instruction length
- Basic instruction set (no floating point)
The general architecture of the core consists of five main modules:
- if_stage: to manage PC and jump when required
- id_stage: to decode instructions and manage registers accordingly
- ex_stage: to execute instructions
- mem_stage: to manage the memory/register before and after the execution of an instruction
- wb_stage: to write back when required
Together all modules perform are an instruction pipeline (the basic instruction cycle is broken up into a series called a pipeline).
The if_stage fetches the instructions. If possible it tries to load an instruction from the cache so it can be executed during the next clock cycle. It also predicts the address of the next instruction. This prediction may be wrong in the case of a taken branch, jump, or exception.
The id_stage decodes the instruction. Once fetched from the instruction cache, and if it is relevant, the instruction bits is shifted down the pipeline.
The ex_stage executes the instructions. It is where the actual computation occurs. This stage is composed of an Arithmetic and Logic Unit, and a bit shifter.
The mem_stage performed memory accesses when required. During this stage, single cycle latency instructions simply have their results forwarded to the next stage.
wb_stage writebacks the result of the execution. During this stage, both single cycle and two cycle instructions write their results into the register file.