Publisher: SynflowStatus: FPGA Proven
SHA-2 is a set of cryptographic hash functions created to secure data. Cryptographic hash functions are mathematical operations run on digital data. A key aspect of cryptographic hash functions is their collision resistance: nobody should be able to find two different input values that result in the same hash output. SHA-256 is a hash functions computed with 32-bit-bit words. The SHA-2 hash function is implemented in some widely used security applications and protocols, including TLS and SSL, PGP, SSH, S/MIME, and IPsec.
The core provides the following features:
- Compliant to FIPS 180-2 specification of SHA-256.
- 264-1 bits maximum message length
- Supported Message lengths multiple of 8-bits
- Direct input and output interfaces, ideal for streaming applications.
- Optimized design for FPGA implementations.
The general architecture of the core consists of four main modules:
- CounterT: this is a "smart" counter
- ComputeW: this module computes W
- ROM: a read only memory to store K
- sha: this module perform the SHA and return the hash.
CounterT is an elaborate counter. It writes the address to the ROM and send data to computeW so that the computed values arrives at the same time to the main SHA loop.
ComputeW is an elaborate 16x32 shift register that compute W from the message send by CounterT. In comparison with a "standard" implementation, tt uses 4 times fewer registers and almost no mux.
sha computes the hash from the data it receives. The W array is computed on-the-fly by ComputeW, and K is send by the ROM during the right clock cycle.