UDP / IP streaming + ARP

Publisher: Synflow

Status: FPGA Proven


Description

The Ethernet UDP/IP Hardware Stack is a high performance, low-latency UDP/IP core compliant with the IEEE-802.3 specification. The core is designed to work with the MAC core. The can offload a processor from the task of UDP/IP encapsulation and enables media streaming over Ethernet. It includes a minimal implementation of ARP to communicate with yoru computer.


Features

The core provides the following features:


Architecture

The general architecture of the core consists of four main modules:


Modules

All modules are implemented in compliance with the IEEE802.3 standard.


Interface

The core is connected directly to the application. The application must be ready to receive data any time and send only frames. The core does not handle segmentation and reassembly.

Status

The project is done and FPGA proven.