UDP / IP streaming + ARP
Publisher: SynflowStatus: FPGA Proven
The Ethernet UDP/IP Hardware Stack is a high performance, low-latency UDP/IP core compliant with the IEEE-802.3 specification. The core is designed to work with the MAC core. The can offload a processor from the task of UDP/IP encapsulation and enables media streaming over Ethernet. It includes a minimal implementation of ARP to communicate with yoru computer.
The core provides the following features:
- Layer 1: IEEE802.3
- Layer 2: IEEE802.3, ARP (Address Resolution Protocol)
- Layer 3: IPv4
- Checksum is computed when sending and receiving frames.
The general architecture of the core consists of four main modules:
- udpTop: this module performs the encapsulation/desencapsulation of frames from/to the application
- ipTop: this module performs the encapsulation/desencapsulation of frames from/to the application
- arpTop: this module manages the ARP protocol
All modules are implemented in compliance with the IEEE802.3 standard.
InterfaceThe core is connected directly to the application. The application must be ready to receive data any time and send only frames. The core does not handle segmentation and reassembly.
The project is done and FPGA proven.